OptiMult

Optimisation of Multipliers for Reconfigurable Logic

The aim of the research project is to develop algorithms for the design of resource- and energy-efficient multipliers for reconfigurable computing systems such as field-programmable gate arrays (FPGAs). Multiplications are among the most basic arithmetic operations, either by themselves or as fundamental building blocks of higher-order arithmetic circuits such as divisions or function approximations. The emergence of reconfigurable computing systems as an important implementation platform requires new concepts, since an architecture-adapted implementation is essential for them. The application areas range from problems that require small word widths (such as in neural networks) to very large word widths (e.g. cryptographic applications). The work proposed here will investigate how the large range of relevant multiplications, ranging from 2 bits to several hundred bits of word length, can be efficiently implemented.